Job Details

Senior SystemVerilog/UVM Verification Engineer - Pre-Silicon

  2025-12-31     US Tech Solutions     Goleta,CA  
Description:

A global staff augmentation firm is seeking a Verification Engineer in California to perform pre-silicon functional verification of high-performance SoCs. The ideal candidate should have strong expertise in UVM and SystemVerilog, and possess a Bachelor's degree in a relevant field. Responsibilities include developing testbenches, debugging complex designs, and automating verification flows. Competitive salary and an equal opportunity work environment offered.#J-18808-Ljbffr


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